SH7720 Datasheet, PDF (295/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
(4) Initial page write exception
• Conditions
A hit occurred to the TLB for a store access, but D = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
H'080
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
Rev. 3.00 Jan. 18, 2008 Page 233 of 1458
REJ09B0033-0300