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SH7720 Datasheet, PDF (334/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Section 8 Interrupt Controller (INTC)
Table 8.4 Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
Priority
Interrupt Interrupt Priority IPR
within IPR Default
Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
NMI
H'1C0*2 16


High
H-UDI
H'5E0*2 15


IRL IRL3 to RL0=B'0000 H'200*3 15


IRL3 to IRL0=B'0001 H'220*3 14


IRL3 to IRL0=B'0010 H'240*3 13


IRL3 to IRL0=B'0011 H'260*3 12


IRL3 to IRL0=B'0100 H'280*3 11


IRL3 to IRL0=B'0101 H'2A0*3 10


IRL3 to IRL0=B'0110 H'2C0*3 9


IRL3 to IRL0=B'0111 H'2E0*3 8


IRL3 to IRL0=B'1000 H'300*3 7


IRL3 to IRL0=B'1001 H'320*3 6


IRL3 to IRL0=B'1010 H'340*3 5


IRL3 to IRL0=B'1011 H'360*3 4


IRL3 to IRL0=B'1100 H'380*3 3


IRL3 to IRL0=B'1101 H'3A0*3 2


IRL3 to IRL0=B'1110 H'3C0*3 1


IRQ IRQ4
H'680*3 0 to 15 (0)
IPRD (3 to 0) 
IRQ5
H'6A0*3 0 to 15 (0)
IPRD (7 to 4) 
TMU TMU_SUNI
H'6C0*3 0 to 15 (0)
IPRD (11 to 8) 
DMAC DEI0
(1)
H'800*3 0 to 15 (0)
IPRE
(15 to 12)
High
DEI1
H'820*3 0 to 15 (0)
DEI2
H'840*3 0 to 15 (0)
DEI3
H'860*3 0 to 15 (0)
Low
LCDC LCDCI
H'900*3 0 to 15 (0)
IPRE (7 to 4) 
SSL SSLI
H'980*3 0 to 15 (0)
IPRE (3 to 0) 
Low
Rev. 3.00 Jan. 18, 2008 Page 272 of 1458
REJ09B0033-0300