SH7720 Datasheet, PDF (400/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn
(BEn) signal for the byte to be written is asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the
CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the
WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.5).
Rev. 3.00 Jan. 18, 2008 Page 338 of 1458
REJ09B0033-0300