SH7720 Datasheet, PDF (477/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
11
RS3
0
R/W Resource Select 3 to 0
10
RS2
0
9
RS1
0
8
RS0
0
R/W
R/W
R/W
Specify which transfer requests will be sent to the DMAC.
The changing of transfer request source should be done
in the state that the DMA enable bit (DE) is set to 0.
0 0 0 0 External request, dual address mode
0 0 0 1 Setting prohibited
0 0 1 0 External request, single address mode
External address space → External device with
DACK
0 0 1 1 External request, single address mode
External device with DACK → External address
space
0 1 0 0 Auto request
0 1 0 1 Setting prohibited
0 1 1 0 Setting prohibited
0 1 1 1 Setting prohibited
1 0 0 0 Selected by DMA extended resource selector
1 0 0 1 Setting prohibited
1 0 1 0 Setting prohibited
1 0 1 1 Setting prohibited
1 1 0 0 Setting prohibited
1 1 0 1 Setting prohibited
1 1 1 0 ADC
1 1 1 1 Setting prohibited
Note: External request specification is valid only in
CHCR_0 and CHCR_1. None of the external
request can be selected in CHCR_2 to CHCR_5.
Rev. 3.00 Jan. 18, 2008 Page 415 of 1458
REJ09B0033-0300