SH7720 Datasheet, PDF(698/1524 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7720 Datasheet, PDF (698/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 18 Serial Communication Interface with FIFO (SCIF)

Table 18.4 SCIF Interrupt Sources

Interrupt Source

DMAC Activation

Interrupt initiated by receive error (ER) or break (BRK)

Not possible

Interrupt initiated by receive FIFO data full flag (RDF) or data ready Possible*1

flag (DR)

Interrupt initiated by receive FIFO data empty flag (TDFE) or transmit Possible*2

data stop flag (TSF)

Notes: 1. DMAC can be activated only by the receive-FIFO-data-full interrupt request.

2. DMAC can be activated only by the transmit-FIFO-data-empty interrupt request.

See section 7, Exception Handling, for priorities and the relationship with non-SCIF interrupts.

Rev. 3.00 Jan. 18, 2008 Page 636 of 1458

REJ09B0033-0300

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