SH7720 Datasheet, PDF (861/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.4.2 Storage Format of the Descriptor
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB
Host Controller must be aligned so that each Dword corresponds to the long-word boundary
(addresses 4n to 4n + 3) of the memory.
24.5 Data Alignment Restriction of USB Host Controller
24.5.1 Restriction on the Line Boundary of the Synchronous DRAM
The transferred data is stored in shared system memory with CPU. The data alignment in system
memory are restricted depends on SDRAM specification which is used as system memory.
DRAM
Row address n
Memory area
(1)
Row address n+1
(2)
Row address n+2
(3)
In above figure, transfer data 1 and 3 are able to be read or written by USB Host Controller. But
transfer data 2 are possibly unable to be read or written by USB Host controller. Any data, which
have possibility to be accessed by USB Host Controller, must be aligned in SDRAM not to cross
row address alignment.
Rev. 3.00 Jan. 18, 2008 Page 799 of 1458
REJ09B0033-0300