SH7720 Datasheet, PDF (47/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 31.20 Operational Flowchart for Commands with Write Data
(Open-ended Multiblock Transfer) (1) ................................................................ 1083
Figure 31.20 Operational Flowchart for Commands with Write Data
(Open-ended Multiblock Transfer) (2) ................................................................ 1084
Figure 31.21 Operational Flowchart for Commands with Write Data
(Pre-defined Multiblock Transfer) (1) ................................................................. 1085
Figure 31.21 Operational Flowchart for Commands with Write Data
(Pre-defined Multiblock Transfer) (2) ................................................................. 1086
Figure 31.22 Operational Flowchart for Commands with Write Data (Stream Transfer) ....... 1087
Figure 31.23 Operational Flowchart for Read Sequence (Single Block Transfer) ................... 1090
Figure 31.24 Operational Flowchart for Read Sequence
(Open-ended Multiblock Transfer) (1) ................................................................ 1091
Figure 31.24 Operational Flowchart for Read Sequence
(Open-ended Multiblock Transfer) (2) ................................................................ 1092
Figure 31.25 Operational Flowchart for Read Sequence
(Pre-defined Multiblock Transfer) (1) ................................................................. 1093
Figure 31.25 Operational Flowchart for Read Sequence
(Pre-defined Multiblock Transfer) (2) ................................................................. 1094
Figure 31.26 Operational Flowchart for Rear Sequence (Stream Read Transfer) .................... 1095
Figure 31.27 Operational Flowchart for Pre-defined Multiblock Read Transfer
in Auto Mode (1) ................................................................................................. 1096
Figure 31.27 Operational Flowchart for Pre-defined Multiblock Read Transfer
in Auto Mode (2) ................................................................................................. 1097
Figure 31.28 Operational Flowchart for Write Sequence (Single Block Transfer) .................. 1100
Figure 31.29 Operational Flowchart for Write Sequence
(Open-ended Multiblock Transfer) (1) ................................................................ 1101
Figure 31.29 Operational Flowchart for Write Sequence
(Open-ended Multiblock Transfer) (2) ................................................................ 1102
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (1) ................................................................. 1103
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (2) ................................................................. 1104
Figure 31.31 Operational Flowchart for Write Sequence (Stream Write Transfer).................. 1105
Figure 31.32 Operational Flowchart for Pre-defied Multiblock Write Transfer
in Auto Mode (1) ................................................................................................. 1106
Figure 31.32 Operational Flowchart for Pre-defied Multiblock Write Transfer
in Auto Mode (2) ................................................................................................. 1107
Section 33 User Break Controller (UBC)
Figure 33.1 Block Diagram of UBC......................................................................................... 1112
Rev. 3.00 Jan. 18, 2008 Page xlvii of lxii