SH7720 Datasheet, PDF (848/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.18 Hc LS Threshold Register (USBHLST)
USBHLST includes an 11-bit value that is used by the host controller to determine whether or not
to authorize the transfer of the LS packed 8 bytes in maximum before EOF. The host controller
and host controller driver cannot change this value.
Bit
Bit Name
31 to 12 
11
LST11
10
LST10
9
LST9
8
LST8
7
LST7
6
LST6
5
LST5
4
LST4
3
LST3
2
LST2
1
LST1
0
LST0
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W LS Threshold
1
R/W This field contains a value to be compared with the FR bit
1
R/W ^{prior to the beginning of low-speed transaction. The}
transaction is started only when the FR bit value is beyond
0
R/W _{the value of the list. The value is calculated by HCD}
0
R/W ^{considering the transmission and set-up overhead.}
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
Rev. 3.00 Jan. 18, 2008 Page 786 of 1458
REJ09B0033-0300