SH7720 Datasheet, PDF (24/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

24.3.13 Hc Done Head ED Register (USBHDHED)......................................................... 781
24.3.14 Hc Fm Interval Register (USBHFI)...................................................................... 781
24.3.15 Hc Frame Remaining Register (USBHFR)........................................................... 783
24.3.16 Hc Fm Number b Register (USBHFN)................................................................. 784
24.3.17 Hc Periodic Start Register (USBHPS) .................................................................. 785
24.3.18 Hc LS Threshold Register (USBHLST) ............................................................... 786
24.3.19 Hc Rh Descriptor A Register (USBHRDA) ......................................................... 787
24.3.20 Hc Rh Descriptor B Register (USBHRDB).......................................................... 789
24.3.21 Hc Rh Status Register (USBHRS)........................................................................ 790
24.3.22 Hc Rh Port Status 1 and Hc Rh Port Status 2 Registers
(USBHRPS1, USBHRPS2) .................................................................................. 792
24.4 Data Storage Format which Required by USB Host Controller ........................................ 798
24.4.1 Storage Format of the Transferred Data ............................................................... 798
24.4.2 Storage Format of the Descriptor.......................................................................... 799
24.5 Data Alignment Restriction of USB Host Controller......................................................... 799
24.5.1 Restriction on the Line Boundary of the Synchronous DRAM ............................ 799
24.5.2 Restriction on the Memory Access Address ......................................................... 800
24.6 Accessing External Address from the USB Host............................................................... 800
24.7 Usage Notes ....................................................................................................................... 801
Section 25 USB Function Controller (USBF) ..................................................... 803
25.1 Features.............................................................................................................................. 803
25.2 Input/Output Pins............................................................................................................... 805
25.3 Register Descriptions......................................................................................................... 806
25.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 808
25.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 810
25.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 811
25.3.4 Interrupt Flag Register 3 (IFR3) ........................................................................... 813
25.3.5 Interrupt Flag Register 4 (IFR4) ........................................................................... 815
25.3.6 Interrupt Select Register 0 (ISR0)......................................................................... 816
25.3.7 Interrupt Select Register 1 (ISR1)......................................................................... 816
25.3.8 Interrupt Select Register 2 (ISR2)......................................................................... 817
25.3.9 Interrupt Select Register 3 (ISR3)......................................................................... 817
25.3.10 Interrupt Select Register 4 (ISR4)......................................................................... 818
25.3.11 Interrupt Enable Register 0 (IER0) ....................................................................... 818
25.3.12 Interrupt Enable Register 1 (IER1) ....................................................................... 819
25.3.13 Interrupt Enable Register 2 (IER2) ....................................................................... 819
25.3.14 Interrupt Enable Register 3 (IER3) ....................................................................... 820
25.3.15 Interrupt Enable Register 4 (IER4) ....................................................................... 820
25.3.16 EP0i Data Register (EPDR0i)............................................................................... 821
Rev. 3.00 Jan. 18, 2008 Page xxiv of lxii