SH7720 Datasheet, PDF (370/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
18
WW2
0
R/W Number of Write Access Wait Cycles
17
WW1
0
R/W Specify the number of cycles that are necessary for write
16
WW0
0
R/W ^access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W Number of Delay Cycles from Address, CSn Assertion to
11
SW0
0
R/W ^{RD, WEn (BEn) Assertion}
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jan. 18, 2008 Page 308 of 1458
REJ09B0033-0300