SH7720 Datasheet, PDF (231/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
(c) P2 Area
The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.
Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with
0s creates the address in the corresponding physical address space.
(d) P4 Area
The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache
and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.
256
H'0000 0000
P0 area
Cacheable
Address translation possible
External Address
Space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
256
U0 area
Cacheable
Address translation possible
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P1 area
Cacheable
Address translation not possible
P2 area
Non-Cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-Cacheable
Address translation not possible
Privileged mode
Address error
Uxy area*
Address error
User mode
H'8000 0000
H'A500 0000
H'A5FF FFFF
H'FFFF FFFF
Note: Only exists when SR.DSP = 1
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)
Rev. 3.00 Jan. 18, 2008 Page 169 of 1458
REJ09B0033-0300