SH7720 Datasheet, PDF (907/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

25.4.4 EP1 Bulk-Out Transfer (Dual FIFOs)
USB function
OUT token reception
Section 25 USB Function Controller (USBF)
Application
Space
in EP1 FIFO?
Yes
No
NAK
Data reception from host
ACK
Set EP1 FIFO full status
(IFR0/EP1 FULL = 1)
Interrupt request
Read EP1 receive data
size register (EPSZ1)
Read data from EP1
data register (EPDR1)
Write 1 to EP1 read
complete bit
(TRG/EP1 RDFN = 1)
Both
EP1 FIFOs empty?
No Interrupt request
Yes
Clear EP1 FIFO full status
(IFR0/EP1 FULL = 0)
Figure 25.11 EP1 Bulk-Out Transfer Operation
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads
without being aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the IFR0/EP1 FULL bit is set. After the first
receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and
so the next packet can be received immediately. When both FIFOs are full, NACK is returned to
the host automatically. When reading of the receive data is completed following data reception, 1
is written to the TRG/EP1 RDFN bit. This operation empties the FIFO that has just been read, and
makes it ready to receive the next packet.
Rev. 3.00 Jan. 18, 2008 Page 845 of 1458
REJ09B0033-0300