SH7720 Datasheet, PDF (1466/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Section 9 Bus State Controller
(BSC)
9.2 Input/Output Pins
Table 9.1 Pin Configuration
Page Revision (See Manual for Details)
283, Amended
284 _{Name I/O Function}
RD/WR O
RD
O
Read/write signal
Connects to WE pins when
SDRAM or byte-selection SRAM is
connected.
Read strobe (read data output
enable signal)
WAIT
I
REFOUT O
A strobe signal to indicate the
memory read cycle when the
PCMCIA is used.
External wait input (sampled at the
falling edge of CKIO)
Bus mastership request signal for
refreshing
9.3.2 Shadow Area
9.4.1 Common Control Register
(CMNCR)
285 Changed
The BSC decodes A28 to A25 of the physical address
and generates chip select signals that correspond to
areas 0, 2 to 4, 5A, 5B, 6A, and 6B.
291 Amended
Bit Initial
Bit Name Value R/W Description
31 to 
16
All 0 R
Reserved
These bits are always read as 0. The
write value should always be 0.
15  0
R
Reserved
This bit is always read as 0. The
write value should always
be 0.
Rev. 3.00 Jan. 18, 2008 Page 1404 of 1458
REJ09B0033-0300