SH7720 Datasheet, PDF (856/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Bit
9
8
7 to 5
Bit Name
LSDA
PPS

Initial
Value R/W Description
0
R/W (Read) Low Speed Device Attached
This bit indicates the speed of the device attached to this
port. When this bit is set, a low-seed device is attached to
this port. When this bit is cleared, a full-speed device is
attached to this port. This bit is valid only when the CCS
bit is set.
0: A full-speed device is set
1: A low-speed device is set
(Write) Clear Port Power
Writing a 1 clears the PPS bit. Writing a 0 has no effect.
1
R/W (Read) Port Power Status
This bit reflects the power state of the port regardless of
the power-switching mode to be executed.
However, because the initial value of the NPS bit of the
USBHRDA is 1, this bit is first fixed to 1. The NPS bit must
first be cleared before the power is switched, as shown
below.
When an over-current condition is detected, this bit is
cleared. Writing SetPortPower or SetGlovalPower sets this
bit. Writing ClearPortPower or ClearGlobalPower clears
this bit. The PSM bit in USBHRDA and the PPCM bit in
USBHRDB determine which power control switch can be
used. Only Set/ClearGlobalPower controls this bit in global
switching mode (PSM= 0). If the PPCM bit of that port is
set in power switching mode (PSM = 1), only the
Set/ClearPortPower command is enabled. If the mask is
not set, the Set/ClearGlovalPowerCommand is enabled.
When the port power is disabled, the CCS, PES, PSS, and
PRS are reset.
0: Port power is off
1: Port power is on
Note: If power switching is not supported, this bit is
always read as 1.
(Write) Set Port Power
Writing a 1 sets the PPS bit. Writing a 0 has no effect.
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 794 of 1458
REJ09B0033-0300