SH7720 Datasheet, PDF (88/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
Classification Symbol
I/O
Clock
XTAL
O
CKIO
I/O
Operating mode MD5 to MD0 I
control
System control RESETP
I
RESETM
I
STATUS1,
O
STATUS0
BREQ
I
BACK
O
Interrupts
CA
I
NMI
I
IRQ5 to IRQ0 I
IRL3 to IRL0 I
Name
Function
Crystal
For connection to a crystal
resonator.
System clock Used as a pin to input external
clock or output clock.
Mode set
Sets the operating mode. Do not
change values on these pins
during operation.
MD2 to MD0 set the clock mode,
MD3 and MD4 set the bus width of
area 0 and MD5 sets the endian.
Power-on reset When low, the system enters the
power-on reset state.
Manual reset
When low, the system enters the
manual reset state.
Status output Indicates the operating state.
Bus request
Bus request
acknowledge
Chip active
Non-maskable
interrupt
Interrupt
requests 5 to 0
Interrupt
requests 3 to 0
Low when an external device
requests the release of the bus
mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which
has output the BREQ signal that it
has acquired the bus.
High in normal operation, and low
in hardware standby mode.
Non-maskable interrupt request
pin. Fix to high level when not in
use.
Maskable interrupt request pins.
Selectable as level input or edge
input. The rising edge or falling
edge is selectable as the detection
edge. The low level or high level is
selectable as the detection level.
Maskable interrupt request pin.
Input a coded interrupt level.
Rev. 3.00 Jan. 18, 2008 Page 26 of 1458
REJ09B0033-0300