SH7720 Datasheet, PDF (224/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
LSB MD: 00
MD: 01
MD: 10
MD: 11
0100 Rm 00MD 0111 LDC.L @Rm+, SR
LDC.L
@Rm+, GBR LDC.L
@Rm+, VBR LDC.L
@Rm+, SSR
0100 Rm 01MD 0111 LDC.L @Rm+, SPC LDC.L
@Rm+, MOD LDC.L
@Rm+, RS LDC.L
@Rm+, RE
0100 Rm
10MD 0111 LDC.L
@Rm+, R0_BANK
LDC.L
@Rm+, R1_BANK
LDC.L
@Rm+, R2_BANK
LDC.L
@Rm+, R3_BANK
0100 Rm
11MD 0111 LDC.L
@Rm+, R4_BANK
LDC.L
@Rm+, R5_BANK
LDC.L
@Rm+, R6_BANK
LDC.L
@Rm+, R7_BANK
0100 Rn Fx 1000 SHLL2 Rn
SHLL8 Rn
SHLL16 Rn
0100 Rn Fx 1001 SHLR2 Rn
SHLR8 Rn
SHLR16 Rn
0100 Rm 00MD 1010 LDS Rm, MACH LDS
Rm, MACL LDS
Rm, PR
0100 Rm 01MD 1010
LDS
Rm, DSR LDS
Rm, A0
0100 Rm 10MD 1010 LDS Rm, X0
LDS
Rm, X1
LDS
Rm, Y0
LDS
Rm, Y1
0100 Rm/Rn Fx 1011 JSR @Rm
TAS.B @Rn
JMP
@Rm
0100 Rn Rm 1100 SHAD Rm, Rn
0100 Rn Rm 1101 SHLD Rm, Rn
0100 Rm 00MD 1110 LDC Rm, SR
LDC
Rm, GBR LDC
Rm, VBR LDC
Rm, SSR
0100 Rm 01MD 1110 LDC Rm, SPC LDC
Rm, MOD LDC
Rm, RS
LDC
Rm, RE
0100 Rm
10MD 1110 LDC
Rm, R0_BANK
LDC
Rm, R1_BANK
LDC
Rm, R2_BANK
LDC
Rm, R3_BANK
0100 Rm
11MD 1110 LDC
Rm, R4_BANK
LDC
Rm, R5_BANK
LDC
Rm, R6_BANK
LDC
Rm, R7_BANK
0100 Rn Rm 1111 MAC.W @Rm+, @Rn+
0101 Rn Rm disp MOV.L @ (disp:4, Rm), Rn
0110 Rn Rm 00MD MOV.B @Rm, Rn MOV.W @Rm, Rn MOV.L @Rm, Rn MOV Rm, Rn
0110 Rn
Rm 01MD MOV.B @Rm+, Rn MOV.W @Rm+, Rn MOV.L @Rm+, Rn NOT
Rm, Rn
0110 Rn Rm 10MD SWAP.B Rm, Rn
SWAP.W Rm, Rn NEGC Rm, Rn
NEG Rm, Rn
0110 Rn Rm 11MD EXTU.B Rm, Rn
EXTU.W Rm, Rn EXTS.B Rm, Rn
EXTS.W Rm, Rn
0111 Rn imm
ADD #imm : 8, Rn
1000 00MD Rn disp MOV.B
R0, @(disp: 4, Rn)
imm
MOV.W
R0, @(disp: 4, Rn)
SETRC #imm
Rev. 3.00 Jan. 18, 2008 Page 162 of 1458
REJ09B0033-0300