SH7720 Datasheet, PDF (659/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt requested when the TDFE flag of SCSSR is
set to 1.
0: Transmit-FIFO-data-empty interrupt request
disabled*
1: Transmit-FIFO-data-empty interrupt request
enabled
Note: * The transmit-FIFO-data empty interrupt
request can be cleared by writing the
greater number of transmit data than the
specified number of transmission triggers
to SCFTDR and by clearing TDFE to 0
after reading 1 from TDFE, or can be
cleared by clearing TIE to 0.
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive-FIFO-data-full
interrupt requested when the RDF flag of SCSSR is
set to1.
0: Receive-FIFO-data-full interrupt request disabled*
1: Receive-FIFO-data-full interrupt request enabled
Note: * The receive-FIFO-data -full interrupt
request can be cleared by reading the
RDF flag after it has been set to 1, then
clearing the flag to 0, or by clearing the
RIE bit to 0.
5
TE
0
R/W Transmit Enable
Enables or disables the SCIF serial transmitter.
0: Transmitter disabled
1: Transmitter enabled*
Note: * The serial mode register (SCSMR) and
FIFO control register (SCFCR) should be
set to select the transmit format and reset
the transmit FIFO before setting the TE bit
to 1.
Rev. 3.00 Jan. 18, 2008 Page 597 of 1458
REJ09B0033-0300