SH7720 Datasheet, PDF (237/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
4.2.2 Page Table Entry Register Low (PTEL)
The page table entry register low (PTEL) register residing at address H'FFFF FFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
Initial
Bit
Bit Name Value R/W Description
31 to 29 
All 0
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 10 PPN

R/W The Number of the Physical Page
9

0
R
Page Management Information
8
V

R/W For more details, see section 4.3, TLB Functions.
7

0
R
6, 5
PR

R/W
4
SZ

R/W
3
C

R/W
2
D

R/W
1
SH

R/W
0

0
R
4.2.3 Translation Table Base Register (TTB)
The translation table base register (TTB) residing at address H'FFFF FFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
4.2.4 MMU Control Register (MMUCR)
The MMU control register (MMUCR) residing at address H'FFFF FFE0. Any program that
modifies MMUCR should reside in the P1 or P2 area.
Rev. 3.00 Jan. 18, 2008 Page 175 of 1458
REJ09B0033-0300