SH7720 Datasheet, PDF (763/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.9 FIFO Control Register (SIFCTR)
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Initial
Bit
Bit Name Value R/W Description
15
TFWM2 0
R/W Transmit FIFO Watermark
14
TFWM1 0
13
TFWM0 0
R/W 000: Issue a transfer request when 16 stages of the
R/W
transmit FIFO are empty.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages of
the transmit FIFO are empty.
101: Issue a transfer request when 8 or more stages of
the transmit FIFO are empty.
110: Issue a transfer request when 4 or more stages of
the transmit FIFO are empty.
111: Issue a transfer request when 1 or more stages of
transmit FIFO are empty.
• A transfer request to the transmit FIFO is issued by
the TDREQ bit in SISTR.
• The transmit FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
12
TFUA4 1
R
Transmit FIFO Usable Area
11
TFUA3 0
10
TFUA2 0
R
Indicate the number of words that can be transferred by
R
the CPU or DMAC as B'00000 (full) to B'10000 (empty).
9
TFUA1 0
R
8
TFUA0 0
R
Rev. 3.00 Jan. 18, 2008 Page 701 of 1458
REJ09B0033-0300