SH7720 Datasheet, PDF (372/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
• CS6AWCR
Initial
Bit
Bit Name Value R/W Description
31 to 13 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W Number of Delay Cycles from Address, CSn Assertion to
11
SW0
0
R/W ^{RD, WEn (BEn) Assertion}
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10
WR3
1
R/W Number of Access Wait Cycles
9
WR2
0
R/W Specify the number of wait cycles that are necessary for
8
WR1
1
R/W ^{read or write access.}
7
WR0
0
R/W ^{0000: 0 cycle}
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Rev. 3.00 Jan. 18, 2008 Page 310 of 1458
REJ09B0033-0300