SH7720 Datasheet, PDF (1463/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
8.3.12 Interrupt Request Register 261
8 (IRR8)
Changed
IRR8 is an 8-bit register that indicates whether interrupt
requests from the SDHI, MMC, and AFEIF are
generated. This register is initialized to H'00 by a
power-on reset or manual reset, but is not initialized in
standby mode.
Note: On the models not having the SDHI, the SDHI-
related bits are reserved. The write value should
always be 0.
Changed and a note added.
Bit
Bit Name Description
0 SDIR SDI Interrupt Request
Indicates whether the SDI (SDHI)
interrupt request is generated.
0: SDI interrupt request is not
generated
1: SDI interrupt request is generated
Note:
On the models not having the
SDHI, this bit is reserved and
always read as 0. The write
value should always be 0.
8.3.13 Interrupt Request Register 262
9 (IRR9)
8.4.3 IRL interrupts
267
Amended
IRR9 is an 8-bit register that indicates whether interrupt
requests from the PCC, USBH, USBF, and CMT are
generated. This register is initialized to H'00 by a
power-on reset or manual reset, but is not initialized in
standby mode.
Deleted
IRL interrupts are included with noise canceller function
and detected when the sampled levels of each
peripheral module clock keep same value for 2 cycles.
This prevents sampling error level in IRL pin changing.
In standby mode, noise canceller is handled by the
RTC clock because the peripheral module clocks are
halted. Therefore, when RTC is not used, recovering to
standby by IRL interrupts cannot be executed in
standby mode.
Rev. 3.00 Jan. 18, 2008 Page 1401 of 1458
REJ09B0033-0300