SH7720 Datasheet, PDF (995/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
27.3.2 A/D Control/Status Registers (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'0000 by a reset and the module standby function and in standby mode.
Bit Bit Name
15 ADF
14 ADIE
Initial Value
0
0
R/W
R/(W)*
R/W
Description
A/D End Flag
Indicates the end of A/D conversion.
[Clearing conditions]
(1) Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
(2) Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion ends cycling through the
selected channels
Scan mode: A/D conversion ends cycling through the
selected channels
Note: Clear this bit by writing 0.
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
Rev. 3.00 Jan. 18, 2008 Page 933 of 1458
REJ09B0033-0300