SH7720 Datasheet, PDF (1117/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.18 FIFO Pointer Clear Register (FIFOCLR)
The FIFO write/read pointer is cleared by writing any value to FIFOCLR.
Initial
Bit
Bit Name Value R/W
7 to 0 FIFOCLR 
W
Description
The FIFO pointer is cleared by writing any value to this
register.
31.3.19 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables/disables a DMA request signal. The
DMA request signal is output by a value that has been set to bits SET2 to SET0.
Set this register before executing a multiblock transfer command (CMD18 or CMD25). Auto
mode cannot be used for open-ended multiblock transfer.
Initial
Bit
Bit Name Value
7
DMAEN 0
6
AUTO 0
5 to 3 
All 0
R/W Description
R/W 0: Disables output of DMA request signal. (Initial value)
1: Enables output of DMA request signal.
R/W This bit is set when the pre-defined multiblock transfer
using DMA transfer is performed in auto mode.
0: Auto mode is not used.
1: Auto mode is used.

Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 1055 of 1458
REJ09B0033-0300