SH7720 Datasheet, PDF (206/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.29 Variation of PDMSB Operation
Mnemonic
PDMSB
Function
MSB detection
Source
Sx

Source 2

Sy
Destination
Dz
Dz
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit is
always cleared. The GT bit always indicates the same state as the DC bit set in signed greater than
mode by the CS[2:0] bits. See the signed greater than mode part above.
3.5.10 Rounding Operation
The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guard-
bit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is
added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the
rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the
variation of this type of operation. The correspondence between each operand and registers is the
same as ALU fixed-point operations as shown in table 3.21.
As shown in figure 3.21, the rounding operation uses full-size data for both source and destination
operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage
is the same stage as the MA stage in which memory access is performed.
The rounding operation is always executed unconditionally, so that the DC, N, Z, V, and GT bits
in DSR are always updated in accordance with the operation result. The definition of the DC bit is
selected by the CS0 to CS2 (condition selection) bits in DSR. The result of these condition code
bits is the same as the ALU-fixed point arithmetic operations.
Rev. 3.00 Jan. 18, 2008 Page 144 of 1458
REJ09B0033-0300