SH7720 Datasheet, PDF (193/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.5.5 ALU Integer Operations
Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of
this type of operation. The correspondence between each operand and registers is the same as
ALU fixed-point operations as shown in table 3.22.
39 31
Guard Source 1
0
39 31
0
Guard Source 2
ALU
GT Z N V DC
DSR
Guard Destination
39 31
0
Ignored
Cleared to 0
Figure 3.14 ALU Integer Arithmetic Operation Flow
Table 3.23 Variation of ALU Integer Operations
Mnemonic
Function
Source 1
Source 2
Destination
PINC
Increment by 1 Sx
+1
Dz
+1
Sy
Dz
PDEC
Decrement by 1 Sx
–1
Dz
–1
Sy
Dz
Note:
The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base
precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts
when a register not providing the guard-bit parts is specified as the source operand. When
a register not providing the guard-bit parts is specified as a destination operand, the upper
word excluding the guard bits of the operation result are input into the destination register.
Rev. 3.00 Jan. 18, 2008 Page 131 of 1458
REJ09B0033-0300