SH7720 Datasheet, PDF (563/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.2 Register Descriptions
The TMU has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and states of these registers in each operating mode. Notation for the CMT registers
takes the form XXX_N, where XXX including the register name and N indicating the channel
number. For example, TCOR_0 denotes the TCOR for channel 0.
(1) Common
• Timer start register (TSTR)
(2) Channel 0
• Timer constant register_0 (TCOR_0)
• Timer counter_0 (TCNT_0)
• Timer control register_0 (TCR_0)
(3) Channel 1
• Timer constant register_1 (TCOR_1)
• Timer counter_1 (TCNT_1)
• Timer control register_1 (TCR_1)
(4) Channel 2
• Timer constant register_2 (TCOR_2)
• Timer counter_2 (TCNT_2)
• Timer control register_2 (TCR_2)
Rev. 3.00 Jan. 18, 2008 Page 501 of 1458
REJ09B0033-0300