SH7720 Datasheet, PDF (63/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
Section 1 Overview
1.1 Features
This LSI is a single-chip RISC microprocessor that integrates a 32-bit RISC-type Super H
architecture CPU with a digital signal processing (DSP) extension as its core, together with a
large-capacity 32-kbyte cache memory, a 16-kbyte X/Y memory, and an interrupt controller.
High-speed data transfers can be performed by an on-chip direct memory access controller
(DMAC), and an external memory access support function enables direct connection to different
kinds of memory. This LSI also supports a stereo audio recording and playback function, a USB
host controller, a function controller, an LCD controller, a PCMCIA interface, an A/D converter,
and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from
an external memory (area 3) can be freely processed. Since the USB host controller, in particular,
conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a device
driver or other devices. Also, low-power operation suitable for battery operation is possible
because the LCD controller continues to display even in sleep mode.
A powerful built-in power management function keeps power consumption low, even during high-
speed operation. This LSI is ideal for electronics devices, which require both high speed and low
power consumption.
The SH7720 group integrates an SSL (Secure Socket Layer) accelerator that performs RSA
(Rivest-Shamir-Adleman) operations and DES (Data Encryption Standard) and Triple-DES
encryption/decryption, while the SH7721 group does not have the SSL accelerator. Each group
consists of several models which includes or does not include an SD host interface (SDHI) to be
suited to a variety of applications. See table 1.2 and 1.3, Product Lineup, for the models including
(or not including) the SDHI.
Note: For the detailed specifications of the SDHI and SSL, contact the Renesas representatives
in your region.
Table 1.1 shows the features of this LSI.
Rev. 3.00 Jan. 18, 2008 Page 1 of 1458
REJ09B0033-0300