SH7720 Datasheet, PDF (759/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
3
TFOVF 0
R/W Transmit FIFO Overflow
0: No transmit FIFO overflow
1: Transmit FIFO overflow
A transmit FIFO overflow means that there has been an
attempt to write to SITDR when the transmit FIFO is full.
When a transmit FIFO overflow occurs, the SIOF
indicates overflow, and writing is invalid.
• This bit is valid when the TXE bit in SICTR is 1.
• When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
2
TFUDF 0
R/W Transmit FIFO Underflow
0: No transmit FIFO underflow
1: Transmit FIFO underflow
A transmit FIFO underflow means that loading for
transmission has occurred when the transmit FIFO is
empty.
When a transmit FIFO underflow occurs, the SIOF
repeatedly sends the previous transmit data.
• This bit is valid when the TXE bit in SICTR is 1.
• When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 3.00 Jan. 18, 2008 Page 697 of 1458
REJ09B0033-0300