SH7720 Datasheet, PDF (412/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Table 9.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 01 (12 bits)
00 (8 bits)
Output Pin of Row Address Column Address Synchronous
This LSI
Output
Output
DRAM Pin
Function
A17
A24
A17
Unused
A16
A23
A16
A15
A23*²
A23*²
A14
A22*²
A22*²
A13 (BA1)
A12 (BA0)
Specifies bank
A13
A21
A12
A20
A13
L/H*¹
A11
A10/AP
Address
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
Unused
A0
A8
A0
Example of connected memory
128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 350 of 1458
REJ09B0033-0300