SH7720 Datasheet, PDF (765/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.10 Clock Select Register (SISCR)
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the
master clock. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified
as B'10 or B'11.
Initial
Bit
Bit Name Value
15
MSSEL 1
14
MSIMM 1
13

0
12
BRPS4 0
11
BRPS3 0
10
BRPS2 0
9
BRPS1 0
8
BRPS0 0
7 to 3 
All 0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
Description
Master Clock Source Selection
0: Uses the input signal of the SIOFMCLK pin as the
master clock
1: Uses Pφ as the master clock
The master clock is the clock input to the baud rate
generator.
Master Clock Direct Selection
0: Uses the output clock of the baud rate generator as the
serial clock
1: Uses the master clock itself as the serial clock
Reserved
This bit is always read as 0. The write value should
always be 0.
Prescalar Setting
Set the master clock division ratio according to the count
value of the prescalar of the baud rate generator.
The range of settings is from B'00000 (× 1/1) to B'11111
(× 1/32).
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 703 of 1458
REJ09B0033-0300