SH7720 Datasheet, PDF (1494/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
Figure 31.21 Operational
1085
Flowchart for Commands with
Write Data (Pre-defined Multiblock
Transfer) (1)
Corrected
Is CRCERI interrupt
Yes
generated?
No
Figure 31.21 Operational
1086
Flowchart for Commands with
Write Data (Pre-defined Multiblock
Transfer) (2)
Corrected (arrow deleted)
Is DRPI interrupt
No
generated?
Yes
No
Is DTBUSY
detected?
Yes
No
TBNCR = n(DRPI)?
Yes
31.5 Operations Using DMAC
No
Notes: 1.
Write data of block length
when block length ≤ FIFO size,
data of FIFO size
when block length > FIFO size.
1093 Corrected
Is BTI interrupt
generated?
Yes
Figure 31.25 Operational
Flowchart for Read Sequence
(Pre-defined Multiblock Transfer)
(1)
Set the number of transfer blocks to TBNCR
Figure 31.27 Operational
Flowchart for Pre-defined
Multiblock Read Transfer in Auto
Mode (1)
1096 Corrected
Write the number of transfer
blocks to TBNCR
31.5.2 Operation of Write
Sequence
1102 Changed
Figure 31.29 Operational
Flowchart for Write Sequence
(Open-ended Multiblock Transfer)
(2)
Yes
Is next block
written?
No
Write 1 to CMDOFF
Execute CMD12
Write 1 to CMDOFF
Execute CMD12
Set DMACR to H'00
FIFO clear
Write 1 to CMDOFF
Command sequence end
Rev. 3.00 Jan. 18, 2008 Page 1432 of 1458
REJ09B0033-0300