SH7720 Datasheet, PDF (118/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
2.5.2 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Instruction
Format
Effective Address Calculation Method
Rn
@Rn
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
@Rn+
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4
+
Calculation Formula

Rn
Rn
After instruction execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 → Rn
Register
indirect with
pre-decrement
@–Rn
1/2/4
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
-
Rn - 1/2/4
1/2/4
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with
Rn after calculation)
Rev. 3.00 Jan. 18, 2008 Page 56 of 1458
REJ09B0033-0300