SH7720 Datasheet, PDF (1101/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
Table 31.4 Correspondence between Command Response Byte Number and RSPR
RSPR Registers
RSPR0
RSPR1
RSPR2
RSPR3
RSPR4
RSPR5
RSPR6
RSPR7
RSPR8
RSPR9
RSPR10
RSPR11
RSPR12
RSPR13
RSPR14
RSPR15
RSPR16
MMC Mode Response
6 Bytes (R1, R1b, R3, R4, R5)
17 Bytes (R2)

1st byte

2nd byte

3rd byte

4th byte

5th byte

6th byte

7th byte

8th byte

9th byte

10th byte

11th byte
1st byte
12th byte
2nd byte
13th byte
3rd byte
14th byte
4th byte
15th byte
5th byte
16th byte
6th byte
17th byte
RSPR0 to RSPR16 are simple shift registers. A command response that has been shifted in is not
automatically cleared, and it is continuously shifted until it is shifted out from the bit 7 in RSPR0.
To clear unnecessary bytes to H'00, write arbitrary values to each RSPR.
• RSPR0 to RSPR16
Bit
7 to 0
Initial
Bit Name Value
RSPR All 0
R/W Description
R/W These bits are cleared to H'00 by writing an arbitrary value.
RSPR0 to RSPR16 are continuous 17-byte shift registers.
Command response is stored.
Rev. 3.00 Jan. 18, 2008 Page 1039 of 1458
REJ09B0033-0300