SH7720 Datasheet, PDF (440/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
(10) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-down mode by
bringing the CKE signal to the low level in the non-access cycle. This power-down mode can
effectively lower the power consumption in the non-access cycle. However, please note that if an
access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the
CKE in order to cancel power-down mode is inserted.
Figure 9.27 shows the access timing in power-down mode.
Power-down Tnop
Tr
CKIO
CKE
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tc1
Td1
Tde
Tap Power-down
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.27 Access Timing in Power-Down Mode
Rev. 3.00 Jan. 18, 2008 Page 378 of 1458
REJ09B0033-0300