SH7720 Datasheet, PDF (543/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
MSTP2 0
R/W Module Stop Bit 2
When the MSTP2 bit is set to 1, the supply of the clock to
the TMU is halted.
0: TMU operates
1: Clock supply to TMU halted
1
MSTP1 0
R/W Module Stop Bit 1
When the MSTP1 bit is set to 1, the supply of the clock to
the RTC is halted.
0: RTC operates
1: Clock supply to RTC halted
0

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
13.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Initial
Bit
Bit Name Value R/W Description
7
MSTP10 0
R/W Module Stop Bit 10
When the MSTP10 bit is set to 1, the supply of the clock
to the H-UDI is halted.
0: H-UDI operates
1: Clock supply to H-UDI halted
6
MSTP9 0
R/W Module Stop Bit 9
When the MSTP9 bit is set to 1, the supply of the clock to
the UBC is halted.
0: UBC operates
1: Clock supply to UBC halted
Rev. 3.00 Jan. 18, 2008 Page 481 of 1458
REJ09B0033-0300