SH7720 Datasheet, PDF (1183/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
31 to 22 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
21
BASMA 0
R/W Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA
are masked or not.
0: All BASRA bits are included in the break conditions
and the ASID is checked
1: All BASRA bits are not included in the break
conditions and the ASID is not checked
20
BASMB 0
R/W Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB
are masked or not.
0: All BASRB bits are included in the break conditions
and the ASID is checked
1: All BASRB bits are not included in the break
conditions and the ASID is not checked
19 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15
SCMFCA 0
R/W L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not
match
1: The L bus cycle condition for channel A matches
14
SCMFCB 0
R/W L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not
match
1: The L bus cycle condition for channel B matches
Rev. 3.00 Jan. 18, 2008 Page 1121 of 1458
REJ09B0033-0300