SH7720 Datasheet, PDF (1264/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 35 I/O Ports
35.11.2 Port L Data Register (PLDR)
PLDR is a register that stores data for pins PTL7 to PTL3. Bits PL7DT to PL3DT correspond to
pins PTL7 to PTL3. When the function is general output port, if the port is read, the value of the
corresponding PLDR bit is returned directly. When the function is general input port, if the port is
read, the corresponding pin level is read.
Initial
Bit Bit Name Value R/W Description
7
PL7DT
0
R/W Table 35.11 shows the function of PLDR.
6
PL6DT
0
R/W
5
PL5DT
0
R/W
4
PL4DT
0
R/W
3
PL3DT
0
R/W
2 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 35.11 Port L Data Register (PLDR) Read/Write Operations
PLCR State
PLnMD1 PLnMD0 Pin State
Read
0
0
Other function PLDR value
1
1
0
1
Note: n = 3 to 7
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PLDR value
Pin state
Pin state
Write
Value is written to PLDR, but does not affect
pin state.
Write value is output from pin.
Value is written to PLDR, but does not affect
pin state.
Value is written to PLDR, but does not affect
pin state.
Rev. 3.00 Jan. 18, 2008 Page 1202 of 1458
REJ09B0033-0300