SH7720 Datasheet, PDF (685/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: Even when the receive error (framing error/parity error) is generated, receive operation is
continued.
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
interrupt request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive data ready
interrupt request is generated.
Note that a common vector is assigned to each interrupt source.
Figure 18.9 shows an example of the operation for reception.
1
Serial
data
Start
bit
0 D0
Parity Stop Start
Data bit bit bit
D1 D7 0/1 1 0 D0
Parity Stop
Data bit bit
1
D1 D7 0/1 1 ^{Idle state}
(mark state)
RDF
FER
Receive-FIFO-data-full
interrupt request
One frame
Data read and RDF Receive-error interrupt
flag read as 1 then request generated
cleared to 0 by
by receive error
receive-FIFO-data-ful
interrupt handler
Figure 18.9 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
When modem control is enabled, transmission can be stopped and restarted in accordance with the
CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark
state after transmission of one frame. When CTS is set to 0, the next transmit data is output
starting from the start bit.
Rev. 3.00 Jan. 18, 2008 Page 623 of 1458
REJ09B0033-0300