SH7720 Datasheet, PDF (557/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

(2) Canceling sleep mode by a power-on reset
Section 13 Power-Down Modes
Reset
CKIO
RESETP ^*1
STATUS
normal ^*4
sleep^*3
Undefined
reset^*2
normal^*4
0 to 10 Bcyc *⁵
Notes: 1. If PLL1 multiplication rate changed by a power-on reset,
RESETP must be kept low for the oscillation stabilization time.
2. reset : HH (STATUS1 = High, STATUS0 = High)
3. sleep : HL (STSTUS1= High, STATUS0= Low)
4. normal : LL (STATUS1 = Low, STATUS0 = Low)
5. Bcyc : Bus clock cycle
0 to 30 Bcyc *⁵
Figure 13.8 STATUS Output When Sleep Mode is Canceled by a Power-on Reset
(3) Canceling sleep mode by a manual reset
Reset
CKIO
RESETM ^*1
STATUS
normal ^*4
sleep^*3
reset^*2
normal^*4
0 to 80 Bcyc *⁵
Notes: 1. RESETM must be kept low until STATAU = reset.
2. reset:HH (STATUS1 = High, STATUS0 = High)
3. sleep:HL(STSTUS1= High, STATUS0= Low)
4. normal:LL (STATUS1 = Low, STATUS0 = Low)
5. Bcyc:Bus clock cycle
0 to 30 Bcyc *⁵
Figure 13.9 STATUS Output When Sleep Mode is Canceled by a Manual Reset
Rev. 3.00 Jan. 18, 2008 Page 495 of 1458
REJ09B0033-0300