SH7720 Datasheet, PDF (784/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
(2) Reception in Master Mode
Figure 21.10 shows an example of settings and operation for master mode reception.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2 Set the SCKE bit in SICTR to 1
3
Start SIOFSCK output
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for
baud rate generator
Output serial clock
4
Set the FSE and RXE bits
in SICTR to 1
5
Store SIOFRXD receive data in SIRDR
synchronously with SIOFSYNC
6
RDREQ = 1?
No
Yes
7
Read SIRDR
Set the start for frame
synchronous signal output and
enable reception
Output frame
synchronous signal
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
Read receive data
Transfer ended? ^No
8
Yes
Clear the RXE bit in SICTR to 0
9
Set the FSE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Set BRDV=111
10
and BPRS=00000 in SISCR
Add pulse (0→1→0)
to the RXRST in SISCR
Reset the master clock source
and baud rate in SISCR
11
Change other _No
transmit mode?
Yes
End
12
Start the setting FSE=0,
TXE=0 and other bit.
Set to disable reception
End reception
Synchronize this LSI internal
frame with FSE=0 if restarting
recept later.
Execute internal initialization
of the bit rate generator
if restarting recept later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
recept mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.
Figure 21.10 Example of Receive Operation in Master Mode
Rev. 3.00 Jan. 18, 2008 Page 722 of 1458
REJ09B0033-0300