SH7720 Datasheet, PDF(1491/1524 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7720 Datasheet, PDF (1491/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Item

Page Revision (See Manual for Details)

31.3.19 DMA Control Register

(DMACR)

1055 Restrictions added

Set this register before executing a multiblock transfer

command (CMD18 or CMD25). Auto mode cannot be

used for open-ended multiblock transfer.

31.4 Operation

1059 Deleted

31.4.1 Operations in MMC Mode

(1) Operation of Broadcast

Commands

â¦In this case, the transfer clock of CLKON should be

divided by 100 and the transfer clock frequency should

be set sufficiently slow.

Corrected and deleted

The individual MMC compares its CID and data on the

MMC_CMD, and if different, aborts CID output. A single

MMC in which the CID can be entirely output enters the

acknowledge state. When the R2 response is

necessary, CTOCR should be set to H'01.

(4) Operation of Commands

without Data Transfer

1062 Corrected

For a command that is related to time-consuming

processing such as flash memory write/erase, the MMC

indicates the data busy state via the MMC_DAT.

â¦

â¢ Whether the data busy state is entered or not is

determined by the DTBUSY bit in CSTR. â¦

Figure 31.5 Example of Command 1064

Sequence for Commands without

Data Transfer (with Data Busy

State)

Changed

(BUSY)

(DTBUSY_TU)

(DTBUSY)

(REQ)

Command sequence execution period

Data busy period

Rev. 3.00 Jan. 18, 2008 Page 1429 of 1458

REJ09B0033-0300

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