SH7720 Datasheet, PDF (612/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Compare Match Timer (CMT)
16.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether the compare match timer counter (CMCNT) is
operated or halted.
Initial
Bit
Bit Name Value R/W Description
15 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
STR4
0
R/W Count Start 4 to 0
3
STR3
0
2
STR2
0
1
STR1
0
0
STR0
0
R/W Selects whether to operate or halt the compare match
R/W ^{timer counter for each channel (CMCNT_4 to CMCNT_0).}
R/W ^{0: CMCNTn count operation halted}
R/W ^{1: CMCNTn count operation}
n: 4 to 0 (corresponds to each channel)
Rev. 3.00 Jan. 18, 2008 Page 550 of 1458
REJ09B0033-0300