SH7720 Datasheet, PDF (1102/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
• RSPRD
Bit
7 to 5
4 to 0
Initial
Bit Name Value

All 0
RSPRD All 0
R/W Description
 Reserved
These bits are always read as 0. The write value should
always be 0.
R/W These bits are cleared to H'00 by writing an arbitrary value.
Command response is stored.
31.3.8 Command Start Register (CMDSTRT)
CMDSTRT triggers the start of command transmission, representing the start of a command
sequence. The following operations should be completed before the command sequence starts.
Command transmission:
• Analysis of prior command response, clearing the command response register write if
necessary
• Analyze/transfer receive data of prior command if necessary
• Preparation of transmission data of the next command if necessary
• Setting of CMDTYR, RSPTYR, TBCR, and TBNCR
CMDR0 to CMDR4, CMDTYR, RSPTYR, TBCR, and TBNCR should not be changed until
command transmission has ended (the CWRE flag in CSTR has been set to 1).
• Setting of CMDR0 to CMDR4
The command sequences are controlled by the sequencers in each MMCIF side and MMC side.
Normally, these operate synchronously, however, these may become temporarily unsynchronized
when an error occurs or when a command is aborted. Take care to set the CMDOFF bit in OPCR,
to issue the CMD12 command, and to process an error in MMC mode. A new command sequence
should be started after confirming that the command sequences on both the MMCIF and MMC
sides have ended.
Rev. 3.00 Jan. 18, 2008 Page 1040 of 1458
REJ09B0033-0300