SH7720 Datasheet, PDF(210/1524 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7720 Datasheet, PDF (210/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 3 DSP Operating Unit

3.5.13 Operand Conflict

When an identical destination operand is specified with multiple parallel instructions, data conflict

occurs. Table 3.34 shows the correspondence between each operand and registers.

Table 3.34 Correspondence between Operands and Registers

X-Memory

Load

Y-Memory 6-Instruction 3-Instruction 3-Instruction

Load

ALU

Multiply

ALU

Ax Ix Dx Ay Iy Dy Sx Sy Du Se Sf Dg Sx Sy Dz

DSP

A0

Registers A1

M0

M1

X0

*2

X1

*2

Y0

Y1

*1

*2

*2 *1

*1

*1

*2 *1 *1 *2 *1

*1

*1

*1

*1 *1

*1

*1

*1 *1

*1

*2 *1 *1

*1

*2

*1

*1

*1

*2

*2

*1 *2 *1 *1

*1 *2

*2

*1

*1

*1 *2

Notes: 1. Registers available for operands

2. Registers available for operands (when there is operand conflict)

There are three cases of operand conflict problems.

â¢ When ALU operation and multiply instructions specify the same destination operand (Du and

Dg)

â¢ When X-memory load and ALU operation specify the same destination operand (Dx and Du,

or Dz)

â¢ When Y-memory load and ALU operation specify the same destination operand (Dy and Du,

or Dz)

In these cases above, the result is not guaranteed.

Rev. 3.00 Jan. 18, 2008 Page 148 of 1458

REJ09B0033-0300

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