SH7720 Datasheet, PDF (806/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
Bit
Bit Name
1
DPE
0
RDEF
Initial Value
0
0
R/W Description
R/W Dial Pulse End
0: Normal state
[Clearing conditions]
• Reset
• Interrupt status 1 is read and then 0 is
written to this bit
1: Dial pulse end interrupt
[Setting conditions]
• Output of all of dial pulse sequences
completed or end command 0H detected
• Illegal end (unspecified dial number and
DPST set when RLYC bit (ACTR2) is low
level)
R/W Ringing Detect
0: Normal state
[Clearing conditions]
• Reset
• Interrupt status 1 is read and then 0 is
written to this bit
1: Ringing waveform detect
[Setting condition]
• Ringing waveform is input to AFE_RDET
pin (Latched at rising edge)
Rev. 3.00 Jan. 18, 2008 Page 744 of 1458
REJ09B0033-0300