SH7720 Datasheet, PDF (743/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.2 Input/Output Pins
The pin configuration in this module is shown in table 21.1.
Table 21.1 Pin Configuration
Channel Pin Name
Abbreviation* I/O
Function
0
SIOF0_MCLK SIOFMCLK
Input Master clock input
SIOF0_SCK
SIOFSCK
I/O
Serial clock
(common to transmission/reception)
SIOF0_SYNC SIOFSYNC
I/O
Frame synchronous signal
(common to transmission/reception)
SIOF0_TxD
SIOFTxD
Output Transmit data
SIOF0_RxD
SIOFRxD
Input Receive data
1
SIOF1_MCLK SIOFMCLK
Input Master clock input
SIOF1_SCK
SIOFSCK
I/O
Serial clock
(common to transmission/reception)
SIOF1_SYNC SIOFSYNC
I/O
Frame synchronous signal
(common to transmission/reception)
SIOF1_TxD
SIOFTxD
Output Transmit data
SIOF1_RxD
SIOFRxD
Input Receive data
Note: * The pins for channel 0 and channel 1 are collectively called SIOFMCLK, SIOFSCK,
SIOFSYNC, SIOFTxD, and SIOFRxD in the following descriptions.
Rev. 3.00 Jan. 18, 2008 Page 681 of 1458
REJ09B0033-0300