SH7720 Datasheet, PDF (1161/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
• Errors during command sequence (data transmission) are detected by the CRC error flag
(CRCERI) or the data timeout error flag. When interrupts are detected, set the CMDOFF bit in
OPCR to 1 to issue the CMD12 command and suspend the command sequence.
• Not in the data busy state is confirmed. If the data busy state is entered, the data busy state is
detected by the data busy end flag (DBSYI).
• After data transfer (after DRPI is detected), check whether the data busy state is entered. If the
data busy state is entered, the end of the data busy state is detected by the data busy end flag
(DBSYI).
• The CMDOFF bit is set to 1 and command sequence is ended.
• When the CRC error (CRCERI) or the command timeout error (CTERI) occurs during
command response reception, write 1 to the CMDOFF bit.
• When the CRC error (CRCERI), write error (WRERI), or the data timeout error (DTERI)
occurs during write data transmission, write 1 to the CMDOFF bit and set DMACR to H'00 to
clear the FIFO.
Note: Access from the DMAC to the FIFO should be performed by byte or longword data.
Rev. 3.00 Jan. 18, 2008 Page 1099 of 1458
REJ09B0033-0300