SH7720 Datasheet, PDF (1393/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

38.4.5 Burst ROM Timing
CKIO
A25 to A0
CSn
RD/WR
RD
T1
Tw
tAD1
tCSD1 tAS
tRWD1
tRSD
D15 to D0
Section 38 Electrical Characteristics
Twx
T2B
Twb
T2B
tAD2
tAD2
tAD2
tCSD1
tRWD1
tRSD
tRDS3
tRDH3
tRDS3
tRDH3
WEn
BS
DACKn*
WAIT
tBSD
tBSD
tDACD
tWTH1
tWTH1
tDACD
tWTS1
tWTS1
Note: * Waveform when active low is specified for DACKn.
Figure 38.19 Read Bus Cycle of Burst ROM
(Software Wait 1, External Wait 1 Input, Burst Wait 1, Number of Burst 2)
Rev. 3.00 Jan. 18, 2008 Page 1331 of 1458
REJ09B0033-0300