SH7720 Datasheet, PDF (90/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
Classification Symbol
I/O
Bus control
CAS
O
DQMUU
O
DQMUL
O
DQMLU
O
DQMLL
O
RAS
O
WAIT
I
IOIS16
I
ICIORD
O
ICIOWR
O
Direct memory DREQ0,
I
access controller DREQ1
(DMAC)
DACK0,
O
DACK1
TEND0,
O
TEND1
16-bit timer pulse TPU_TO3 to O
unit (TPU)
TPU_TO0
TPU_TI3A to I
TPU_TI2A
TPU_TI2B to I
TPU_TI3B
Analog front end AFE_RLYCNT O
interface (AFEIF)
AFE_FS
I
AFE_SCLK
I
Name
Function
Column address Connect to the CAS pin when the
SDRAM is connected.
DQ mask UU Selects D31 to D24. (SDRAM)
DQ mask UL Selects D23 to D16. (SDRAM)
DQ mask LU Selects D15 to D8. (SDRAM)
DQ mask LL
Row address
Selects D7 to D0. (SDRAM)
Connect to the RAS pin when the
SDRAM is connected.
Wait input
Inserts a wait cycle into the bus
cycles during access to the
external space.
16-bit IO
Indicates 16-bit I/O when PCMCIA
is in use.
IO read
Indicates I/O read when PCMCIA
is in use.
IO write
Indicates I/O write when PCMCIA
is in use.
DMA-transfer Input pins for external requests for
request
DMA transfer
DMA transfer
request
reception
Indicates the acceptance of DMA
transfer requests to external
devices.
DMA-transfer Transfer end output pins for DMAC
end
TPU compare- TPU compare-match output pins
match output
TPU clock input TPU clock input pins
TPU clock input TPU clock input pins
AFE on-hook On-hook control pin
control
AFE frame
AFE frame synchronization signal
synchronization pin
AFE shift clock AFE shift clock input pin
Rev. 3.00 Jan. 18, 2008 Page 28 of 1458
REJ09B0033-0300