SH7720 Datasheet, PDF (778/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Table 21.6 Audio Mode Specification for Transmit Data
Mode
Monaural
Stereo
Left and right same audio output
Note: x: Don't care
TDLE
1
1
1
Bit
TDRE
0
1
1
TLREP
x
0
1
Table 21.7 Audio Mode Specification for Receive Data
Bit
Mode
RDLE
RDRE
Monaural
1
0
Stereo
1
1
Note: Left and right same audio mode is not supported in receive data.
To execute 8-bit monaural transmission or reception, use the left channel.
(2) Control Data
Control data is written to or read from by the following registers.
• Transmit control data write: SITCR (32-bit access)
• Receive control data read: SIRCR (32-bit access)
Figure 21.6 shows the control data and bit alignment in SITCR and SIRCR.
(a) Control data: One channel
31
24 23
16 15
87
0
Control data
(channel 0)
(b) Control data: Two channels
31
24 23
16 15
87
0
Control data
(channel 0)
Control data
(channel 1)
Figure 21.6 Control Data Bit Alignment
Rev. 3.00 Jan. 18, 2008 Page 716 of 1458
REJ09B0033-0300